[Pl-seminar] 4/7 Seminar: Rachit Nigam "Compiler Infrastructure for Accelerator Generators"
michelledt.neu at gmail.com
Fri Apr 1 16:42:28 EDT 2022
NUPRL Seminar Presents
1:30PM to 2:30PM
Thursday, April 7th, 2022
Room 366 WVH and Zoom (https://northeastern.zoom.us/j/98598689387?pwd=Z0tyT2FFdFVsZGFKbDltMjRhS095Zz09)
Compiler Infrastructure for Accelerator Generators
Specialized, application-specific hardware accelerators are chipping away at the dominance of traditional, general-purpose CPUs. We need to make it possible for domain experts—not just hardware experts—to harness the efficiency of hardware specialization for the computations they care about. Domain-specific languages (DSLs) for building hardware accelerators offer a way to raise the level of abstraction in hardware design from gates, wires, and clock cycles. Unfortunately, building a new hardware DSL is a gargantuan task requiring not only the design of new abstractions, but also supporting tools such as an optimizing compiler, testing, and debugging infrastructure.
Our solution is Calyx (calyxir.org), an intermediate language and a compiler infrastructure that can represent, optimize, and lower accelerators to synthesizable hardware designs. By targeting Calyx instead of a traditional hardware design language, designers can build new DSLs and generate a custom hardware accelerator without needing hardware expertise.
Rachit Nigam (rachitnigam.com) is PhD candidate at Cornell University interested in programming languages, computer architectures, and compilers that turn programs to architectures.
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