[Colloq] Invited talk by Lieven Eeckhout Friday 11/6 @ 11:30

[Rachel Kalweit]

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    Department of Electrical and Computer Engineering Lecture Series
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Title:
Interval Simulation: Raising the Level of Abstraction in Architectural 
Simulation

Location: 442 Dana Research Center
Time: Friday 11/6 @ 11:30-1

Speaker:
Prof. Lieven Eeckhout, Ghent University, Belgium

Abstract:

Detailed architectural simulators suffer from a long development cycle and 
extremely long evaluation times. This longstanding problem is further 
exacerbated in the multicore processor era. Existing solutions address the 
simulation problem by either sampling the simulated instruction stream or by 
mapping the simulation models on FPGAs; these approaches achieve substantial 
simulation speedups while simulating performance in a cycle-accurate manner.

This talk proposes interval simulation which takes a completely different 
approach: interval simulation raises the level of abstraction and replaces the 
core-level cycle-accurate simulation model by a mechanistic analytical model. 
The analytical model estimates core-level performance by analyzing intervals, 
or the timing between two miss events (branch mispredictions and TLB/cache 
misses); the miss events and their latencies are modeled through simulation of 
the memory hierarchy, cache coherence protocol, interconnection network and 
branch predictor. By raising the level of abstraction, interval simulation 
reduces both development time and evaluation time.

Our experimental results using the SPEC CPU2000 and PARSEC benchmark suites and 
the M5 simulator, show good accuracy (average error around 4.6% and max error 
around 11% for multi-threaded full-system workloads) while achieving a one 
order of magnitude simulation speedup compared to cycle-accurate simulation. 
Moreover, interval simulation is easy to implement: our implementation of the 
mechanistic analytical model incurs only one thousand lines of code. Its high 
accuracy, fast simulation speed and ease-of-use make interval simulation a 
useful complement to the architect's toolbox for exploring system-level and 
high-level micro-architecture trade-offs in early stages of the design.


Bio:
Lieven Eeckhout is on the faculty of the Department of Electronics
and Information Systems at Ghent University, Belgium. His main research 
interests include computer architecture in general, and performance modeling 
and analysis, simulation methodology, and workload characterization in 
particular. He served as the program chair for ISPASS 2009, and is the general 
chair for ISPASS 2010. His work on hardware performance counter architectures 
was selected by IEEE Micro Top Picks from 2006 Computer Architecture 
Conferences as one of the "most significant research publications in computer 
architecture based on novelty and industry relevance".

Host: David Kaeli, kaeli at ece.neu.edu
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= Prof. David Kaeli   email: kaeli at ece.neu.edu phone: 617-373-5413  =
=    ECE Dept.   318 Dana Research Center, NEU, Boston, MA 02115    =
=               URL:  www.ece.neu.edu/faculty/kaeli.html            =
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