[Colloq] CCIS and The Colleege of Engineering hosts: Shubu Mukherjee, Intel 366 WVH TODAY 1/7/05

[Rachel Kalweit]

College of Computer and Information Science and The College of 
Engineering Colloquium
Presents:
Shubu Mukherjee, Intel

Who will speak on:
Computing Architectural Vulnerability Factors

Friday, January 7, 2005
12:00pm
366 West Village H
Northeastern University

ABSTRACT
With each technology generation, we are starting to see a dark side to
Moore's Law in which the increased functionality we get with our
exponentially increasing number of transistors is being countered with
an exponentially increasing radiation-induced soft error rate. This will
take increasing effort and cost to cope with. In this talk I will
describe the severity of the soft error problem as well as techniques to
estimate a processor's soft error rate. These estimates should help
designers choose appropriate error protection schemes for various
structures within a microprocessor. A key aspect of our soft error
analysis is that some single-bit faults (such as those occurring in the
branch predictor) will not produce an error in a program's output. We
define a structure's architectural vulnerability factor (AVF) as the
probability that a fault in that particular structure will result in an
error in the final output of a program. A structure's error rate is the
product of its raw error rate, as determined by process and circuit
technology, and the AVF. Using this methodology, we are systematically
computing the AVF of various processor structures, such as instruction
queue, execution units, caches, translation buffers, and store buffer.
This analysis also provides new insight into how to reduce a structure's
AVF and thereby reduce the overall soft error rate of a processor.

Biography
Shubu Mukherjee is the Manager and Technical Leader of Intel's FACT
group in Hudson, Massachusetts. The Fault Aware Computing Technology
(FACT) group is involved with various aspects of soft error measurement,
detection, and recovery techniques in current and future machines. In
the past, he worked for Digital Equipment Corporation for ten days and
Compaq Computer Corporation for three years. In Compaq, he worked on
fault tolerance techniques for Alpha processors and was one of the
architects of the Alpha 21364 interconnection network. He received his
B.Tech. from the Indian Institute of Technology, Kanpur and M.S. and PhD
from the University of Wisconsin-Madison. He has received a number of
achievement awards in the past few years. More details about his work at
http://www.cs.wisc.edu/~shubu.



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