[PRL] Multicore talk at MIT Th 11/8/07

[Mitchell Wand]

From: CSAIL Event Calendar <eventcalendar at csail.mit.edu>
To: seminars at csail.mit.edu
Date: Mon, 29 Oct 2007 10:33:46 -0400
Subject: TALK:Thursday 11-8-07 Dataflow and Tiles: Two Great MIT Tastes that
Go Great Together (Bulldozers, Termites, and Chainsaws: Finding a Gradual
Path to Parallelism)

Dataflow and Tiles: Two Great MIT Tastes that Go Great Together (Bulldozers,
Termites, and Chainsaws: Finding a Gradual Path to Parallelism)
CSAIL Colloquium 2007-2008
Speaker: Doug Burger
Speaker Affiliation: The University of Texas at Austin
Host: Arvind
Host Affiliation: CSAIL

Date: 11-8-2007
Time: 4:00 PM - 5:00 PM
Refreshments: 3:45 PM
Location: 32-G449(Patil)

Abstract:

The transition to multicore is effectively an industrial gamble that
application programmers will start writing all of their code in parallel, or
that workloads will change to make it simple to generate many threads.  A
key question for architects is the granularity of the processors on each
multicore chip -- many small processors (termites), a few medium-sized
processors (chainsaws), or fewer large behemoths (bulldozers).  In this
talk, I will show that with an EDGE instruction set, this choice is a false
choice, since we are able to build chainsaws and bulldozers out of termites.
 I will describe Composable Lightweight Processors, a new class of design
that allows larger logical processors to be synthesized out of smaller ones,
transparent to application software.  This class of architectures "borrows"
two techniques pioneered by MIT: Dataflow and tiled architectures, and
combines them to create wonderful new capabilities.  EDGE-based CLPs treat
large processors as a distributed system made up of many small pieces on an
on-chip micronetwork.  This approach creates the opportunity to have many
intermediate design points between traditional uniprocessors and
multiprocessors, which may facilitate a more gradual--and
graceful--transition to explicit parallelism.

Bio:

Doug Burger is an Associate Professor of Computer Sciences at the University
of Texas at Austin.  He received his B.S. in Computer Science from Yale
University, and Ph.D. in Computer Sciences from the University of
Wisconsin-Madison.  His research interests include computer architecture,
supercomputing, compiler design and implementation, as well as the
implications of nanometer-scale computing technologies.  He co-leads the
TRIPS project at UT-Austin, which has prototyped a full system consisting of
aggressive, 16-wide out-of-order issue cores using Explicit Data Graph
Execution (or EDGE) instruction sets.  He is a Senior Member of the IEEE and
ACM, Chair of ACM SIGARCH, and was the recipient of the 2006 ACM Maurice
Wilkes
Award.

Relevant URL(S):
For more information please contact: Colleen Russell, 3-0145,
crussell at csail.mit.edu
-------------- next part --------------
HTML attachment scrubbed and removed